Job Description

Job Type : Contract 12 months +

Location/City : CA - Santa Clara

Category : Electrical

Region : Pacific

Id : 25662

ASIC  Design Verification Engineer

Hours/Week: 40 hours/week, M-F
Start Date: ASAP
Assignment Length: 12 months
Location: Santa Clara, CA



* Verify complex design blocks using equally complex SV/UVM verification environments
* Develop and execute pre-silicon verification test plans
* Develop and enhance scoreboard checks and stimulus
* Develop directed and random verification tests to validate block and IP functionality
* Develop verification components and tools
* Develop verification functional coverage using industry standard coverage analysis tools/methods
* Debug regression fails
* Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

Required Skills and Experience:
* 5 or more years of proven verification experience on large ASIC development projects in a hardware development setting
* Strong background in SystemVerilog and UVM verification methodologies
* Strong debug skills and experience with debug tools such as DVE/Verdi
* Proficiency in Object Oriented programming, computer architecture and data structures
* Strong analytical/problem solving skills and pronounced attention to details
* Strong interpersonal and communication skills
* Must be comfortable working across geographies


How to Apply:
Please send your resume in Word or PDF format to:
Copy and Paste the following job title and code and place it in the subject line of your email so we can identify the job: ASIC Design Verification Engineer (#25662-MH1639)

Application Instructions

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