Job Description

Job Type : Contract 6-12 month

Location/City : MA - Boxborough

Category : Hardware

Region : Northeast

Id : 25814

ASIC DFT Engineer

Hours/Week: 40 hours/week, M-F
Start Date: ASAP
Assignment Length: 6+ months
Location: Boxborough, MA



  • Implementation and verification of DFT architecture and features
  • Scan/Jtag/boundary scan insertion and ATPG pattern generation
  • ATPG patterns verification with gate level simulation
  • Test coverage and test cost reduction analysis
  • Post silicon support to ensure successful bringup and enhance yield learning

Required Experience:

  • Ability to debug large complex scan drc and gate level simulation issues at SoC level
  • Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, ? etc)
  • Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
  • Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design
  • Excellent oral, written and interpersonal communication skills

How to Apply:
Please send your resume in Word or PDF format to:
Copy and Paste the following job title and code and place it in the subject line of your email so we can identify the job: ASIC DFT Engineer (#25814-MH1639)

Application Instructions

Please click on the link below to apply for this position. A new window will open and direct you to apply at our corporate careers page. We look forward to hearing from you!

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