Job Description

Job Type : Contract 3-6 month

Location/City : CA - Santa Clara

Category : Hardware

Region : Pacific

Id : 25395

ASIC Physical Design Engineer

Hours/Week: 40 hours/week, M-F
Start Date: ASAP
ignment Length: 4+ months

Location: Santa Clara, CA



Chip Level Static Timing Analysis, Constraints analysis and Timing closure activities including ECO implementation to fix timing issues on post route database


Strong STA skills including PrimeTime/PrimeTime SI for static timing analysis, Perl/tcl programming experience is a plus



SoC Architecture; knowledge and hands-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces.


An ideal candidate would also exhibit:

Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership


How to Apply:
Please send your resume in Word or PDF format to:
Copy and Paste the following job title and code and place it in the subject line of your email so we can identify the job: ASIC Physical Design Engineer (#25395-MH1639)

Application Instructions

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