Job Description

Digital Systems-on-Chip Architect, RTL Design

Contract 40 hours weekly 12-18 months

Security Requirement: Applicants selected for this position will be required to obtain and maintain a government security Government security clearance requires proof of US citizenship

Client is seeking talented and motivated individuals to develop cutting-edge future computing systems architectures, which will be used in autonomously navigated vehicles implementing AI and machine vision algorithms. The ideal candidate will have experience in digital front-end design and will be able to translate systems requirements into an SoC topology using System C or C++, develop power and test models, and drive the design to verified RTL. Applicants should have experience with design flows from Cadence or Synopsys, and have a working knowledge of physical, as well as logical, design

Specific Responsibilities: ¿ Requirements capture ¿ System architecture development ¿ IP block configuration ¿ RTL design in SystemVerilog, Verilog or VHDL ¿ Functional verification ¿ Handoff to physical design ¿ Experience in multi-core processor systems ¿ Fluent in Verilog/VHDL/System C ¿ Fluent in Cadence or Synopsys Digital ASIC Tool Suite ¿ Ability to acquire a security clearance if needed Desired Qualifications: ¿ PhD or MSEE with 25+ years of experience ¿ Experience working with firmware developers. ¿ Experience with GPU & neural network inferencing subsystems ¿ Familiarity with sensor & multi-media subsystems ¿ Familiarity with hardware security, e.g., encryption, key management, TRNG/DRNG, PUFs, root-of-trust, design obfuscation, etc.

Familiarity with analog ASICs: Voltage and Current sources, Amplifiers, Converters, PLLs, and Transceivers

Application Instructions

Please click on the link below to apply for this position. A new window will open and direct you to apply at our corporate careers page. We look forward to hearing from you!

Apply Online