Job Description

Digital Systems-on-Chip Architect

Contract 40 hours weekly, 12-18+ months

Remote work is not an option, Applicants selected for this position will be required to obtain and maintain a government security Government security clearance requires proof of US citizenship

** Client has implemented a mandatory COVID-19 vaccination requirement for all employees. This will be a condition of employment to work at Client.

Client seeking talented and motivated individuals to develop cutting-edge future computing systems architectures, which will be used in autonomously navigated vehicles implementing AI and machine vision algorithms. The ideal candidate will have experience in digital front-end design and will be able to translate systems requirements into an SoC topology using System C or C++, develop power and test models, and drive the design to verified RTL. Need someone to work onsite. Remote work is not an option.

Applicants should have experience with design flows from Cadence or Synopsys, and have a working knowledge of physical, as well as logical, design. Specific Responsibilities: ¿ Requirements capture ¿ System architecture development ¿ IP block configuration ¿ RTL design in SystemVerilog, Verilog or VHDL ¿ Functional verification ¿ Handoff to physical design

Experience in multi-core processor systems ¿ Fluent in Verilog/VHDL/System C ¿ Fluent in Cadence or Synopsys Digital ASIC Tool Suite ¿ Ability to acquire a security clearance if needed Desired Qualifications: ¿ PhD or MSEE with 25+ years of experience ¿ Experience working with firmware developers. ¿ Experience with GPU & neural network inferencing subsystems ¿ Familiarity with sensor & multi-media subsystems ¿ Familiarity with hardware security, e.g., encryption, key management, TRNG/DRNG, PUFs, root-of-trust, design obfuscation, etc.

Familiarity with analog ASICs: Voltage and Current sources, Amplifiers, Converters, PLLs, and Transceivers Security Requirement

Application Instructions

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