Job Description


Six month assignment - Monday - Friday, 40 hours 
 

This Senior Design Engineer position will be responsible for working with other FPGA engineers in a team environment developing and verifying FPGA designs for closed control-loop motion control applications.

Experience with FPGA/ ASIC VHDL design. Experience with other design or verification languages is a plus.
Experience with VHDL based self-checking FPGA/ASIC test benches
Experience with FPGA/ASIC designs for control loops.
Experience interfacing FPGAs/ASICs to ADCs, DACs, LVDTs, resolvers, temperature sensors, and common standard communication busses (MIL-STD-1553, RS-422, Ethernet).
Experience with Microsemi, Modelsim, and Synplify design tools. Experience integrating FPGAs/ASICs with the circuit card level and box-level designs in a laboratory environment.
Experience with FPGA/ASIC design lifecycle phases/processes and coding standards is a plus.

 

BSEE and 20 years or MSEE and 15 years of FPGA or ASIC design and verification experience.

Application Instructions

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