Job Description

PLL Circuit Design Engineer
Contract 12+ Months
Mon – Fri 40 hours/week
*100% Remote Work Available

About the Job

Our client develops high-performance computing and visualization products to solve some of the world’s toughest and most interesting challenges. We are searching for an PLL Circuit Design Engineer who will join the fast-growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering our products.
 

Compensation, Benefits, and Culture – What’s in it for you?

  • Good compensation aligned with current market rates. Get paid weekly.
  • Opportunity work with an outstanding ASIC development company.
  • Blue Cross Blue Shield health insurance, Dental insurance, 401k, accrued Paid Time Off, etc.
  • Enthusiastic, bright, and talented individuals collaborating on ideas

Responsibilities:

  • Design of building blocks of a PLL including architecture development and transistor level circuit design
  • Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
  • Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution

Required Qualifications:

  • Masters degree in Electrical Engineering or equivalent preferred
  • 5-8 years of professional experience in the semiconductor industry
  • Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
  • Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
  • Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis.
  • Solid knowledge Analog Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers etc.
  • Solid knowledge of industry standard tools and practices for analog circuit design
  • Good knowledge in Physical design, STA, methodology scripts (Tcl)
  • Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
  • Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
  • High-frequency design experience
  • Possess strong analytical/problem solving skills and pronounced attention to details
  • Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy
These skills are nice to have:
  • Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
  • Proficiency in scripting languages like Perl, Python, MATLAB etc. is a plus.


It is the policy of GCR to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, protected veteran or disabled status, or genetic information. GCR is an Equal Opportunity/Affirmative Action Employer and embraces diversity in our employee population.

Application Instructions

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