RTL Design Engineer
Hours/Week: 40 hours/week, M-F
Start Date: ASAP
Assignment Length: 9+ months
Location: Boxborough, MA
- Perform IP source code development integrating external IP from ARM and Cadence processors while adding custom logic for an exciting new project.
- Perform RTL design using Verilog
- 6+ years of RTL design experience using Verilog is required
- Experience integrating external IP from ARM into an ASIC is required
- Experience coding RTL for custom IP development is required
- Understands the system level, including general concepts of operating system software and hardware interactions
- Experience working with Cadence Digital Signal Processing (DSP) logic is a plus.
- Experience working on IP blocks with 1 million+ gates is a plus.
- Experience integrating ARM Coresight is a plus
It is the policy of GCR to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, protected veteran or disabled status, or genetic information. GCR is an Equal Opportunity/Affirmative Action Employer and embraces diversity in our employee population.
Job Status: Contract/Temporary