RTL Design Engineer
RTL Design Engineer
Contract 6+ Months
Mon – Fri 40 hours/week
*U.S. remote working, Easter Time Zone is preferred
About the Job
Our client develops high-performance computing and visualization products to solve some of the world’s toughest and most interesting challenges. We are searching for an RTL Design Engineer who will focus on owning and creating complex circuitry in RTL for development of a graphics processor unit (GPU) resulting in a fast, low power, efficient, best in class ASIC.
Compensation, Benefits, and Culture – What’s in it for you?
- Good compensation aligned with current market rates. Get paid weekly.
- Opportunity work with an outstanding ASIC development company.
- Blue Cross Blue Shield health insurance, Dental insurance, 401k, accrued Paid Time Off, etc.
- Enthusiastic, bright, and talented individuals collaborating on ideas
- Collaborate with system and IP level architects to understand the features to be implemented and document the low-level hardware architecture
- Create design documentation, accounting for interactions with other features and the existing hardware system, both your block and the neighboring blocks
- Implement the design in Verilog or System Verilog, ensuring adherence to our RTL coding guidelines
- Creating a design that has high-performance, low power, minimum area, and can execute with a very high clock frequency
- Improve existing designs to improve performance and clock frequency, while reducing area and power
- Run and analyze reports and resolve issues from: linting, timing, synthesis, and formal verification.
- Assist debugging test failures in both simulation, emulation, and silicon environments
- Create SystemVerilog cover-points and assertions to allow verification and full functional coverage of your code. Review code coverage, and work with DV to achieve code coverage closure.
- BS degree in Electrical or Computer Engineering (MS degree preferred)
- Having ~10 years of ASIC design experience
- Proficient in writing efficient RTL code in Verilog and System Verilog including use of a source control system and RTL linting tools
- Proficient in debugging RTL code using simulation tools, including the ability to determine if the root cause of a failing test is the firmware, hardware, or test issue
- Engineering tools experience with VCS, Spyglass, DC, and Formality
- Experience in Graphics IP pipeline is a plus
It is the policy of GCR to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, protected veteran or disabled status, or genetic information. GCR is an Equal Opportunity/Affirmative Action Employer and embraces diversity in our employee population.
Job Status: Contract/Temporary