Job Description

Sr. Digital Design Verification Engineer

Contract 40 hours weekly, 12-18 months M-F 40 hours

Security Requirement:

At a minimum, the ability to obtain a US secret clearance is required which requires proof of US citizenship. * Active secret clearance is preferred.


Work on-site in the Cambridge office is expected, with opportunities to perform design work from home as programs allow.

Digital Design Team is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications. You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

Required Qualifications: * BS degree with 8 years¿ experience * Fluent in SystemVerilog including SVA * Recent experience with UVM * Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS) * Firm grasp of constrained-random and coverage-driven verification * Experience with formal analysis * Practice using Python, Perl, Bash or other scripting languages * Ability to work in a Linux environment * Strong analysis and problem-solving skills Preferred Qualifications: * Experience leading verification teams *

Experience with analog or mixed-signal simulations (AMS)

Application Instructions

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